connect_debug_cores - 2024.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2024-05-30
Version
2024.1 English

Connect debug slave instances to the master instance. A valid master is a debug bridge or debug hub instance configured in "From BSCAN To DebugHUB" mode. A valid slave could be any of the following debug cores (Ex: ILA, VIO, JTAG_to_AXI). connect_debug_cores can only connect master and slave instances that exist in the same region (either in Reconfigurable Partition or static)

Syntax

connect_debug_cores ‑master <args> ‑slaves <args> [‑quiet] [‑verbose]

Returns

Debug master and slave instances.

Usage

Name Description
-master A valid debug bridge or debug hub instance configured in "From BSCAN To DebugHUB" mode. Only one master instance is allowed.
-slaves List of valid slave instances. A valid slave instance is any of the following debug cores (Ex: ILA, VIO, JTAG_to_AXI)
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution

Categories

Debug, XDC

Description

Connect debug slave instances to the specified master instance. The command can add the specified slaves into an existing debug chain, where the specified slaves will be connected to the debug hub or bridge, without affecting debug slaves that are already in the connection chain.

Debug masters include both the Debug Hub and Debug Bridge. The AMD Vivado™ Debug Hub core provides an interface between the JTAG Boundary Scan (BSCAN) interface of the device and the Vivado Debug cores, including the Integrated Logic Analyzer (ILA), Virtual Input/Output (VIO), and the JTAG-to-AXI. The Vivado Debug Bridge is a debug controller that provides multiple options to communicate with the debug cores in both flat designs, or Partial Reconfiguration (PR) designs. The Debug Bridge can be configured to debug designs using a JTAG cable, or remotely through Ethernet, PCIe, or other interfaces using a Xilinx™ Virtual Cable (XVC), without the need for a JTAG cable. Refer to the Vivado Design Suite User Guide: Vivado Programming and Debugging (UG908) for more information.

Important: For Partial Reconfiguration (PR) designs, the connect_debug_cores command can only connect master and slave instances that occur in the Static Region, or in the same Reconfigurable Partition.

Arguments

-master <arg> - (Required) A valid debug hub instance, or debug bridge, configured in From BSCAN To Debug HUB mode for PR designs. Only one master can be specified.

-slaves <args> - (Required) A list of one or more debug core slave instances. A valid slave instance is an ILA, VIO, or JTAG_to_AXI debug core.

Note: If any of the specified slaves is already connected to another master, it is first disconnected from the current master and reconnected to the new master.
-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

Examples

The following example connects the specified ILA cores to the debug bridge:

connect_debug_cores -master [get_cells inst_count/debug_bridge_0] \
-slaves [list [get_cells inst_count/ila_0] [get_cells inst_count/ila_1] ]