config_flows - 2024.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2024-05-30
Version
2024.1 English

Config Flow

Syntax

config_flows [‑mark_debug <arg>] [‑quiet] [‑verbose]

Usage

Name Description
[-mark_debug] Allows nets with MARK_DEBUG to be optimized instead of preserved.
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution

Categories

Project

Description

This command configures tool behavior, it spans multiple stages of the Vivado core design flow, from IP integrator to bitstream generation. The user selection affects synthesis, constraints, and HW debug.

Arguments

-mark_debug - (Optional) Allow optimization of nets with MARK_DEBUG instead of preserve. This includes both HDL attributes and XDC constraints. This setting makes it easier to move in and out of the design debug phases. The setting must be applied before opening and launching design runs or before opening design checkpoints. The following three values are supported:

  • enable - Do not optimize MARK_DEBUG nets. This is default value.
  • disable - Allow both synthesis and implementation to freely optimize MARK_DEBUG nets.
  • synthesis_only - Synthesis will not optimize MARK_DEBUG nets so that they are available at the beginning of implementation, but MARK_DEBUG nets can be freely optimized during implementation.