report_scopes - 2024.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2024-05-30
Version
2024.1 English

Print names of the children scopes (declarative regions) of given scope(s) or the current scope

Syntax

report_scopes [‑quiet] [‑verbose] [<hdl_scopes>...]

Returns

Report_scopes prints a subset of properties of the HDL scope on console in textual format.

Usage

Name Description
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
[<hdl_scopes>] The hdl_objects to report. Default is report_scopes [get_scopes *]

Categories

Description

Reports the names and types of HDL Scopes in the current scope of the current simulation, or of specified scopes.

An HDL Scope is a declarative region of an HDL file, where objects are declared. The following are examples of HDL Scopes in Verilog and VHDL:

  • Verilog scopes: module, function, task, process, other begin-end blocks
  • VHDL scopes: entity/architecture pair, block, function, procedure, process

You must have an open simulation to use this command.

Arguments

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<hdl_scopes> - (Optional) Specifies the scopes upon which to report. The default is the current scope.

Examples

The following example reports the children scopes of /tb/UUT:

report_scopes [get_scopes /tb/UUT/* filter {type==module}

The following example reports the children scopes of the current scope:

report_scopes
         VHDL Instance: {U_DEBOUNCE_0}
         VHDL Instance: {U_DEBOUNCE_1}
         VHDL Instance: {U_SINEGEN}
         VHDL Instance: {U_FSM}
          VHDL Process: {line__138}
          VHDL Process: {line__184}
          VHDL Process: {line__185}
          VHDL Process: {line__186}
          VHDL Process: {line__187}
          VHDL Process: {line__191}