lock_design - 2024.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2024-05-30
Version
2024.1 English

Locks or unlocks netlist, placement or routing of a design. The 'lock/unlock' will only applied on physically placed cells and routed nets

Syntax

lock_design [‑level <arg>] [‑unlock] [‑export] [‑quiet] [‑verbose] [<cell>]

Usage

Name Description
[-level] specify the locking and unlocking level; Valid values are logical, placement, and routing. Default: placement
[-unlock] Unlock cells, if cells are not specified, whole design is unlocked; '-level' parameter must be specified for unlocking.
[-export] mark that the constraints can be exported.
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
[<cell>] Lock cells, if cells are not specified, whole design is locked. Notice only placed cells and routed nets will be locked. Default: *

Categories

Project

Description

This command is used in the Hierarchical Design Flows for Design Preservation and Dynamic Function eXchange (DFX). Refer to the Vivado Design Suite User Guide: Hierarchical Design (UG905) for more information on these design flows, and the use of this command.

The lock_design command is used to lock down the placement and/or routing of a design, or of the specified cell of a design. After reading in an Out-of-Context (OOC) design checkpoint using the read_checkpoint command, the preservation level for the module must be defined.

This command sets the IS_LOC_FIXED, IS_BEL_FIXED, and IS_ROUTE_FIXED properties of the specified logic.

Arguments

-level <arg> - (Optional) Specify the level of the cell or design to preserve in the current design. As a default, the placement data is preserved. Accepted values are:

  • logical - Preserves the logical design. Any placement or routing information is still used, but can be changed if the tools can achieve better results.
  • placement - Preserves the logical and placed design. Any routing information is still used, but can be changed if the tools can achieve better results. This is the default setting.
  • routing - Preserves the logical, placed and routed design. Internal routes are preserved, but interface nets are not. In order to preserve routing, the CONTAIN_ROUTING property must have been used on the Pblock during the OOC implementation. This ensures that there will be no routing conflicts when the OOC implementation is reused.

-unlock - (Optional) Unlock cells. If cells are not specified, the whole design is unlocked. The -level option must be specified for unlocking, just as it was for locking.

Tip: Locking -level routing locks the logical, placement, and routing data of the design. However -unlock -level routing only unlocks the routing data. You must use -unlock -level logical to unlock the routing, placement, and logical data of the design.

-export - (Optional) Permit the export the placement and routing data as an XDC file. The constraints of a locked design or cell can be exported using the write_xdc command. By default, the constraints of a locked design or cell cannot be exported.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<cell> - (Optional) Lock the specified cells in the design, if cells are not specified, the whole design is locked. The default is to lock all cells in the design.

Tip: Only placed cells and routed nets will be locked at the level specified.

Examples

The following example locks the netlist, placement, and routing data for the specified cells of the current design:

lock_design -level routing [get_cells usbEngine*]

This example unlocks the routing data for the specified cells of the current design, while leaving the netlist and placement data locked from the prior example:

lock_design -unlock -level routing [get_cells usbEngine*]

The following example unlocks the routing, placement, and netlist data for the specified cells of the current design:

lock_design -unlock -level logical [get_cells usbEngine*]