iphys_opt_design - 2024.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2024-05-30
Version
2024.1 English

Interactive phys_opt_design.

Syntax

iphys_opt_design [‑fanout_opt] [‑critical_cell_opt] [‑replicate_cell]
    [‑reconnect] [‑placement_opt] [‑forward_retime] [‑backward_retime]
    [‑net <arg>] ‑cluster <args> ‑place_cell <args> [‑dsp_register_opt]
    [‑bram_register_opt] [‑uram_register_opt] [‑shift_register_opt]
    [‑cell <arg>] [‑packing] [‑unpacking] [‑port <arg>] [‑critical_pin_opt]
    [‑restruct_opt] [‑equ_drivers_opt] [‑skipped_optimization]
    [‑create_bufg] [‑insert_negative_edge_ffs] [‑hold_fix]
    [‑slr_crossing_opt] [‑shift_register_to_pipeline] [‑auto_pipeline]
    [‑pipeline_to_shift_register] [‑control_set_opt] [‑memory_rewire_opt]
    [‑quiet] [‑verbose]

Usage

Name Description
[-fanout_opt] Fanout optimization including very high fanout optimizations
[-critical_cell_opt] Do cell-duplication based optimization on timing critical nets
[-replicate_cell] Atomic cell replication operation, for interconnect retiming and LUT optimizaton
[-reconnect] Reconnect loads from equivalent drivers for interconnect retiming and LUT optimization
[-placement_opt] Move cells to reduce delay on timing-critical nets
[-forward_retime] Forward retiming optimization
[-backward_retime] Backward retiming optimization
[-net] net to be optimized
-cluster Clusters of load pins
-place_cell Place cell or cell connecting to pin to loc
[-dsp_register_opt] DSP register optimization
[-bram_register_opt] BRAM register optimization
[-uram_register_opt] UltraRAM register optimization
[-shift_register_opt] Shift register optimization
[-cell] cell to be optimized
[-packing] Packing in DSP/BRAM
[-unpacking] Unpacking in DSP/BRAM
[-port] Port in DSP/BRAM that is optimized
[-critical_pin_opt] Pin Swap optimization
[-restruct_opt] LUT restructuring optimization
[-equ_drivers_opt] Equivalent driver rewiring
[-skipped_optimization] The change is not committed
[-create_bufg] Insert bufg to drive HFO nets
[-insert_negative_edge_ffs] Inserting negative edge triggered FFs for high hold mitigation
[-hold_fix] Inserting buffers for hold fix optimization
[-slr_crossing_opt] Optimize slr crossing nets
[-shift_register_to_pipeline] shift register to pipeline opt
[-auto_pipeline] Auto pipeline
[-pipeline_to_shift_register] pipeline_to_shift_register
[-control_set_opt] Control set optimization
[-memory_rewire_opt] Memory rewire optimization
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution

Categories

Tools

Description

The iphys_opt_design command describes a specific optimization that was performed by the phys_opt_design command, such as replicating a critical cell or pulling registers from a block RAM to improve critical path delay. The iphys_opt_design command includes all the information necessary to recreate both the post-optimization logical netlist and the placement changes required for the optimized netlist.

Interactive physical optimization can be used in two ways:

  • Applying post-placement physical optimizations to the pre-placement netlist to improve the overall placement result and improve design performance.
  • Saving the physical optimizations in a Tcl script to be repeated as needed.

The various optimizations performed by phys_opt_design can be written to an iphys_opt Tcl script by write_iphys_opt_tcl, and read into the design by the read_iphys_opt_tcl command.

Tip: The iphys_opt_design command is intended for use inside the iphys_opt Tcl script file. These commands can be edited in the context of the iphys_opt Tcl script, but they are not intended to be specified at the command line.

This command returns a transcript of its processes, or an error if it fails.

Arguments

-fanout_opt - (Optional) Performs delay-driven optimization on the specified net, by replicating drivers to reduce delay.

-critical_cell_opt - (Optional) Replicate cells on specified nets to reduce delays.

-placement_opt - (Optional) Move cells to reduce delay on specified nets.

-rewire - (Optional) Refactor logic cones to reduce logic levels and reduce delay on critical signals.

-net <arg> - (Optional) Specify the net to apply an optimization to.

-cluster <args> - (Required) Specify a cluster of load pins.

-place_cell <args> - (Required) Place the specified cells, or cells connected to the specified pins, on the device sites specified.

-dsp_register_opt - (Optional) Improve critical path delay by moving registers from slices to DSP blocks, or from DSP blocks to slices.

-bram_register_opt - (Optional) Improve critical path delay by moving registers from slices to block RAMs, or from block RAMs to slices.

-uram_register_opt - (Optional) Improve critical path delay by moving registers from slices to UltraRAMs, or from UltraRAMs to slices.

-shift_register_opt - (Optional) Perform shift register optimization to improve timing on negative slack paths between shift register cells (SRLs) and other logic cells.

-cell <arg> - (Optional) Specify a cell to apply an optimization to.

-packing - (Optional) Packing in DSP/Block RAM.

-unpacking - (Optional) Unpacking in DSP/Block RAM.

-port <arg> - (Optional) Specify a port on a cell to apply the optimization to.

-critical_pin_opt - For LUT inputs, this optimization performs remapping of logical pins to physical pins, also known as pin-swapping, to improve critical path timing.

-skipped_optimization - (Optional) Defines the specified optimization as not performed. These are optimizations identified by phys_opt_design that are skipped because suitable locations for optimized logic cannot be found. For example, Block RAM register optimizations to improve slack that are skipped because no suitable locations can be found for the registers.

-insert_negative_edge_ffs - (Optional) Insert negative edge, or falling edge triggered flip flops to help manage hold timing.

-hold_fix - (Optional) Performs optimizations to insert data path delay buffers for hold fix optimization.

-slr_crossing_opt - (Optional) Performs post-place or post-route optimizations to improve the path delay of inter-SLR connections. The optimization adjusts the locations of the driver, load, or both along the SLR crossing after potential replication. For use with UltraScale™ and UltraScale+™ devices.

-auto_pipeline - (Optional) Auto pipeline the design.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

Examples

The following example performs a critical cell optimization on the specified net and cluster of ports:

iphys_opt_design -critical_cell_opt -net \
   {ADUR_CORE_INST/CPE_INST/CPE_ANT_RESOURCE_TDM_INST0 \
   /CPE_ANT_LINE_IQ_TDM_ANT0_INST/CPE_PN_MULT_INST/CPE_PN_MUL_INST3 \
   /Q_PNI_MULT_INST/pn_mult_reg[3][0]} \
   -cluster {pn_mult[3]_i_14_replica  {\
   {ADUR_CORE_INST/CPE_INST/CPE_ANT_RESOURCE_TDM_INST0 \
   /CPE_ANT_LINE_IQ_TDM_ANT0_INST/CPE_PN_MULT_INST/CPE_PN_MUL_INST2 \
   /Q_ADD_INST/pn_mult_reg[3]_i_6_CARRY8/S[0]}}}\
   -cluster {pn_mult[3]_i_14_replica_1  {\
   {ADUR_CORE_INST/CPE_INST/CPE_ANT_RESOURCE_TDM_INST0 \
   /CPE_ANT_LINE_IQ_TDM_ANT0_INST/CPE_PN_MULT_INST/CPE_PN_MUL_INST0 \
   /Q_ADD_INST/pn_mult_reg[3]_i_10_CARRY8/S[0]}}}\

The following example performs a shift register optimization on the specified cell:

iphys_opt_design -shift_register_opt -cell \
   {ADUR_CORE_INST/EMIF_INTERFACE_INST/EMIF_HOST_IF_INST/DLY_INST1 \
   /PD_INST_FPGA/delay_chain_reg[9][16]_srl9} -port D