create_debug_port - 2024.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2024-05-30
Version
2024.1 English

Create a new debug port

Syntax

create_debug_port [‑quiet] [‑verbose] <name> <type>

Returns

New debug_port object.

Usage

Name Description
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
<name> Name of the debug core instance
<type> Type of the new debug port

Categories

Debug, XDC

Description

Defines a new port to be added to an existing Vivado™ ILA debug core that was added to the design using the create_debug_core command. The port provides connection points on an ILA core to attach nets from the design for debugging.

When a new debug core is created using the create_debug_core command, it includes a clk and probe port by default. However, you can add trigger input/output port types as well. Refer to the Vivado Design Suite User Guide: Programming and Debugging (UG908) for more information on port types and purpose.

A port can have one or more connection points to support one or more nets to debug. As a default new ports are defined as having a width of 1, allowing only one net to be attached. You can change the port width of probe ports to support multiple signals using the set_property port_width command (see Examples).

Note: clk, trig_in, trig_in_ack, trig_out, and trig_out_ack ports can only have a width of 1.

You can connect signals to ports using the connect_debug_port command, modify existing probe connections using modify_debug_ports, and disconnect signals with the disconnect_debug_port command.

Arguments

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<name> - (Required) The name of the ILA debug core to add the new port to. The debug core must already exist in the project having been created with create_debug_core.

<type> - (Required) The type of debug port to insert. The supported port types are:

  • clk - Defines the clock port for connecting the ILA debug core to a clock domain. Each debug core can only have one clk port, and each clk port can only connect to one clock domain. Therefore you must use multiple ILA cores to probe signals from different clock domains.
    Important: Ensure that the connected clocks are free-running clocks. Failure to do so could result in an inability to communicate with the debug core when the design is loaded onto the device.
  • probe - Provides probe points to connect to signals that are marked for debugging with the MARK_DEBUG property. The ILA debug core can contain multiple probe ports, which are automatically numbered by the Vivado tool when the port is added to the core. Each probe port can contain one or more channels, or connection points, as defined by the PORT_WIDTH property.
  • trig_in/trig_in_ack, and trig_out/trig_out_ack - The ILA probe trigger comparators used to detect specific comparison conditions on the probe inputs to the ILA core. trig_in and trig_in_ack, and trig_out and trig_out_ack should be added to the debug core as port pairs when used. Refer to the Vivado Design Suite User Guide: Programming and Debugging (UG908) for more information.

Examples

The following example creates a new debug core, and then adds an additional probe port to the core, then sets the width of that new port to 8, and connects signals to the probe port:

create_debug_core myCore ila
create_debug_port myCore probe
set_property PORT_WIDTH 8 myCore/probe1
connect_debug_port -channel_start_index 1 myCore/probe1 \
{m1_cyc_i m1_ack_o m1_err_o m1_rty_o}
Note: Recall that the ILA core is created with a clk and probe port by default, so the new probe port is automatically numbered as probe1.