Vivado IP Integrator Block Automation - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English
The AMD Versalâ„¢ adaptive SoC PHY for PCI Express IP supports IP integrator block automation to easily connect the GT_QUADs on IP integrator canvas. The following steps shows using the IP integrator block automation.
  1. Create an IP integrator block design from Vivado project as shown in the following figure.

  2. Add the Versal Adaptive SoC PHY for PCI Express IP to the canvas as shown in following figure.

  3. Configure the Versal Adaptive PHY for PCI Express IP by opening the IP GUI (double click on IP symbol) using steps mentioned in Customizing the Core section.
  4. Click on Run Block Automation from Designer Assistance BAR as shown in above figure.
  5. The Versal Adaptive PHY for PCI Express IP will be connected to GT Quads (inside pcie_phy_Versal_0_support) and the required ports will be made external as shown in the following figure.