Performance and Resource Use - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English

Resources required for the Versal™ Adaptive SoC PHY for PCIe® IP are mentioned in the following table. These values are generated using AMD Vivado™ Design Suite for the supported devices.

Table 1. Device Utilization
Family Speed Lane LUTs FFs
Versal™ Adaptive SoC PHY for PCIe® Gen1 x1 21 226
Gen2 x1 21 226
Gen3 x1 21 226
Gen4 x1 21 226
Gen5 (Versal Premium only) x1 21 226
Gen1 x2 41 411
Gen2 x2 41 411
Gen3 x2 41 411
Gen4 x2 41 411
Gen5 (Versal Premium Only) x2 41 411
Gen1 x4 81 781
Gen2 x4 81 781
Gen3 x4 81 781
Gen4 x4 81 781
Gen5 (Versal Premium only) x4 81 781
Gen1 x8 161 1553
Gen2 x8 161 1553
Gen3 x8 161 1553
Gen4 x8 161 1553
Gen1 x16 321 3097
Gen2 x16 321 3097
Gen3 x16 321 3097