GT Selection and Pin Planning for Versal Premium - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English

This appendix provides guidance on gigabit transceiver (GT) selection for AMD Versal™ Premium devices and some key recommendations that should be considered when selecting the GT locations. This appendix provides guidance for CPM5 (Versal Adaptive SoC CPM mode for PCI Express® ), PL PCIE5 (Versal Adaptive SoC Integrated Block for PCI Express) and Versal Adaptive SoC PHY for PCI Express. In this appendix, the PL PCIE5 Versal Premium device PHY for PCIe IP related guidance is of primary importance, while the other related guidance might be relevant and is provided for informational purposes.

A GT Quad is comprised of four GT lanes. When selecting GT Quads for the PHY IP based solution with an AMD PCIE MAC, AMD recommends that you use the GT Quads most adjacent to the AMD PCIE macro. While this is not required, it improves place, route, and timing for the design.

  • Link widths of x1, x2, and x4 require one bonded GT Quad and should not split lanes between two GT Quads.
  • A link width of x8 requires two adjacent GT Quads that are bonded and are in the same SLR.
  • A link width of x16 requires four adjacent GT Quads that are bonded and are in the same SLR.
  • Link speed of 32 Gb/s supports link widths of x1,x2 and x4.
  • The PL PCIE5 blocks should use GTs adjacent to the PCIe block where possible.
  • CPM5 has a fixed connectivity to GTs based on the CPM configuration.

The GTYPs associated with CPM5 are dedicated for CPM5 use case. They are not available for use for PL PCIE5 and the Versal Premium Adaptive SoC PHY for PCI Express.

The remaining GTYPs in the device are available for use for PL-based solutions. PL PCIE5 and Versal Premium Adaptive SoC PHY for PCI Express.

The PCIe reference clock uses GTREFCLK0 in the PCIe lane 0 GT Quad for x1, x2, x4, and x8 configurations. For x16 configurations, the PCIe reference clock should use GTREFCLK0 on a GT Quad associated with lanes 8-11. This allows the clock to be forwarded to all 16 PCIe lanes.

The PCIe reset pin for PL PCIE5 and Versal Premium Adaptive SoC PHY for PCI Express designs can be connected to any compatible single-ended PL IO pin location. For CPM5, the reset IO pin for each CPM5 PCIE controller should be independently driven.