Introduction - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English

The AMD Versal™ Adaptive SoC PHY for PCIe® IP is a building block IP that allows for a PCI Express® MAC to be built as soft IP in the device fabric. The Versal adaptive SoC PCIe PHY IP design cannot be migrated to AMD UltraScale™ or AMD UltraScale+™ parts.

Note: IP supports AMD Vivado™ IP integrator flow. The GT Quads are always outside the PHY for PCIe IP and connected in IP integrator block design.