Advanced Settings Tab - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English
Figure 1. Advanced Settings Tab
Enable Slot Clock Configuration
When this option is selected, the link is synchronously clocked, that is, whether the device reference clock would be provided synchronously by the connector or asynchronously through an onboard PLL.
TX Preset
It is not advisable to change the default value of 4. Preset value of 5 might work better on some systems.
Use AMD MAC
Select this option if the connected PCIe MAC to the Versal PHY IP is a AMD MAC. Selecting this option removes soft TX and RX equalization modules which are not required for AMD PCIe MACs. De-selecting the option enables TX and RQ equalization modules required for third party PCIe MACs. For third-party PCIe MACs, de-select this option to enable the TX and RX equalization modules needed.
Form factor driven Insertion loss adjustment
Indicates the transmitter to receiver insertion loss at the Nyquist frequency depending on the form factor selection. There are three available options: Chip to Chip, Add-in Card, and Backplane in the menu, corresponds to 5 dB, 20 dB, and 20 dB insertion loss respectively.
Receiver Detect
Indicates the type of Receiver Detect Default or Falling Edge. For more information about this option, see the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).
ASPM Support Option
The available options are No_ASPM, L0s Supported and L1 Supported. Select the option that is the same as that supported in the MAC. ASPM L0s is available only for Gen1 and Gen2 configurations.