The following features are not supported in the Versal Premium adaptive SoC PHY for PCI Express:
- Lane 0 (master) must not be powered down or de-activated.
- Per-lane power down is not supported.
- PIPE low power state of P0s is not supported when the max speed is configured as Gen3, Gen4, or Gen5.
- PIPE low power state of P2 is not supported.
- Bypassing the RX elastic buffer is not supported.
- Gen3, Gen4, and Gen5 equalization settings are not preserved after the rate change.
- PCIe PHY does not check or monitor for PIPE protocol errors.
- Only GTYPs not dedicated to CPM5 are available for use for PL use cases. For more information, see GT Selection and Pin Planning for Versal Premium.
- PCIe beacon transmit and receive is not supported.