The following features are not supported in the Versal Premium adaptive SoC PHY for PCI Express:
- Lane 0 (master) must not be powered down or de-activated.
- Per-lane power down is not supported.
- PIPE low power state of P0s is not supported when the max speed is configured as Gen3, Gen4, or Gen5.
- PIPE low power state of P2 is not supported.
- Bypassing the RX elastic buffer is not supported.
- Gen3, Gen4, and Gen5 equalization settings are not preserved after the rate change.
- PCIe PHY does not check or monitor for PIPE protocol errors.
- Only GTYPs not dedicated to CPM5 are available for use for PL use cases. For more information, see GT Selection and Pin Planning for Versal Premium.
- PCIe beacon transmit and receive is not supported.
- This IP architecture assumes exclusive use of one or more complete GT quads, regardless of the designed link width. While it might be possible to share unused lanes in the GT quad with other instances of this IP, non-PCIe IPs, or custom GT-based interfaces for x2 and x1 link widths, AMD does not support evaluations or implementations of such sharing arrangements. The feasibility of sharing depends on the specific GT configuration required for other protocols, links, and lanes intended to share the GT quad. Factors affecting GT configuration include external REFCLKs, fabric design clocks and resets, GT clock management resources, connectivity rules, mode, and electrical settings.