PIPE RX Margin (To MAC) - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English
Table 1. PIPE RX Margin (To MAC)
Name Width Direction Clock Domain Description
pipe_rx_margin_res_req 1 output pclk RX Margin Response Request. When 1b, data presented on pipe_rx_margin_res_{*} signals to MAC is valid. GT Quad drives pipe_rx_margin_req_req to 1b then waits for pipe_rx_margin_res_ack to be driven 1b, before driving it to 0b.
pipe_rx_margin_res_ack 1 input pclk RX Margin Response Ack. 1b indicates MAC has accepted data presented on pipe_rx_margin_res_{*} signals to a GT Quad, and 1b in response to pipe_rx_margin_res_req being 1b. pipe_rx_margin_res_ack is driven to 0b, when pipe_rx_margin_res_req transitions to 0b.
pipe_rx_margin_res_lane_num 2 output pclk RX Margin Response Lane Number. Physical Lane Number in a GT Quad for which data has been received in the range 0H-3H.
pipe_rx_margin_res_cmd 4 output pclk RX Margin Response Command. This is the command in response to request generated by GT Quad.
pipe_rx_margin_res_payload 8 output pclk RX Margin Response Payload. This is payload returned by GT Quad in response.