Example Design - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English

This chapter contains information about the example design provided in the AMD Vivado™ Design Suite.

The example design is a design assistant to validate the functionality of the Versal™ Adaptive SoC PHY for PCI Express® core. It ensures the connectivity, clock connections, reset sequence, and enablement of rate change based on your selection.