PIPE RX Margin (To GT Quad) - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English
Table 1. PIPE RX Margin (To GT Quad)
Name Width Direction Clock Domain Description
pipe_rx_margin_req_req 1 output pclk RX Margin Response Request. When 1b, data presented on pipe_rx_margin_req_{*} signals to a GT Quad is valid. MAC drives pipe_rx_marginn_req_req to 1b then waits for pipe_rx_marginn_req_ack to be driven 1b, before driving it to 0b.
pipe_rx_margin_req_ack 1 input pclk RX Margin Request Ack. 1b indicates GT Quad has accepted data presented on pipe_rx_margin_req_{*} signals to a GT Quad, and 1b in response to pipe_rx_margin_req_req being 1b. pipe_rx_margin_req_ack is driven to 0b, when pipe_rx_margin_req_req transitions to 0b.
pipe_rx_margin_req_lane_num 2 output pclk RX Margin Request Lane Number. Physical Lane Number in a GT Quad for which data has been received in the range 0H-3H.
pipe_rx_margin_req_cmd 4 output pclk RX Margin Request. This is the Margin Command received in CSKPOS on Upstream Port or Margin Command from Lane Margin Control Register on Downstream Port.
pipe_rx_margin_req_payload 8 output pclk RX Margin Request Payload. This is the RX Margin Payload received in CSKPOS on Upstream Port or Step Margin Value.