TX Driver Signal Interface Ports - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

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1.0 English
Table 1. TX Driver Signals for Gen1 and Gen2
Name Width Direction Clock Domain Description
phy_txmargin[2:0] 3 Input pclk Selects TX voltage levels. The recommendation is to set this port to 000b for the normal operating voltage range.
  • 000b: Programmable (default)
  • 001b: Programmable
  • 010b: Programmable
  • 011b: Programmable
  • 100b: Programmable
  • 101b: Programmable
  • 110b: Programmable
  • 111b: Programmable
phy_txswing 1 Input pclk Controls TX voltage swing level. Gen1 and Gen2 only.
  • 0b: Full swing (default)
  • 1b: Low swing
phy_txdeemph 1 Input pclk Selects TX de-emphasis. Gen1 and Gen2 only.
  • 0b: -6.0 dB de-emphasis
  • 1b: -3.5 dB de-emphasis (default)