Versal Premium Adaptive SoC PHY for PCI Express - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English

The Versal™ Adaptive SoC PHY for PCI Express® IP Core internally does not instantiate the GTYP transceiver like the UltraScale or UltraScale+ PHY for PCIe IP. GT Quads in Versal premium adaptive SoC are always external to the PHY IP and they can also connect to the PHY IP. GT Quads are highly configurable and tightly integrated with the programmable logic resources.

The Versal™ Adaptive SoC PHY for PCI Express® core by default is configured to work with AMD PCIe MAC using phy_use_xilinx_mac attribute set to true. Setting phy_use_xilinx_mac to true, bypasses TX equalization and RX equalization modules as these are present in the AMD PCIe MAC wrapper. For using this core with a third party MAC IP, you need to set phy_use_xilinx_mac attribute set to false. Setting phy_use_xilinx_mac to false, includes TX equalization and RX equalization modules in the PHY wrapper.