Versal Adaptive SoC PHY for PCI Express Unsupported Features - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English

The following features are not supported in the core:

  • Powering down of lane 0 (master) is not supported.
  • Per-lane power down is not supported.
  • PIPE low power state of P0s is not supported when the max speed is configured as Gen3 or Gen4.
  • PIPE low power state of P2 is not supported.
  • Bypassing the RX elastic buffer is not supported.
  • Preserving of Gen3/Gen4 equalization settings is not supported after the rate change.
  • PCIe PHY does not check or monitor for PIPE protocol errors.
  • Checking or monitoring for PIPE protocol errors is not supported.
  • Tandem Configuration is not available or applicable for this core. For 100 ms enumeration of PCIe end points, the CPM mode for PCI Express must be used; for more information, see Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346). PL-based PCIe cores, as described in Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343), does not support Tandem Configuration at this point.