Versal Adaptive SoC PHY for PCI Express Features - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English
  • Gen1 (2.5 GT/s), Gen2 (5.0 GT/s), Gen3 (8.0 GT/s), and Gen4 (16.0 GT/s) speeds are supported.
  • Versal devices support:
    • 2.5 GT/s, 5.0 GT/s, and 8.0 GT/s line rates with x1, x2, x4, x8, and x16 lane operation.
      Note: x16 lane width support is dependent the on available GTYP in the selected device/package.
    • 16.0 GT/s line rate with x1, x2, x4, and x8 lane operation.
  • GT Quad is always outside the PHY IP and it is available in the IP integrator block design on opening the example design.
  • Supports PIPE low power state of P0s only at Gen1 or Gen2 speeds. PIPE P0s are equivalent to MAC LTSSM state of L0s.
  • Supports synchronous and asynchronous applications.
  • Rate change between Gen1 and Gen2 is a fixed datapath implementation.
  • Transceiver reset sequence is part of the GT Quad in Versal devices as compared to UltraScale and UltraScale+.
  • There is no option to choose the GT Quad location in the PHY IP GUI. You are expected to LOC the suitable GT Quad in the top level constraints file (XDC).