Basic Tab - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English

The initial customization screen is used to define the basic parameters for the core, including the component name, reference clock frequency, lane width, and speed.

Figure 1. Basic Tab
Component Name
It is the base name of the output files generated for the core. The name must begin with a letter and can be composed of these characters: a to z, 0 to 9, and "_."
Link Width
The core requires the selection of the initial lane width. Supported lane widths are x1, x2, x4, x8, and x16.
Maximum Link Speed
The core allows you to select the Maximum Link Speed supported by the device. Supported link speeds are:
  • 2.5 Gb/s, 5.0 Gb/s, 8.0 Gb/s, and 16.0 Gb/s. The 16.0 Gb/s is available only for lane widths of x1, x2, x4, and x8.
  • 32.0 Gb/s link speed is available for GTYP enabled Versal devices. The x1, x2, and x4 lane widths are available with 32.0 Gb/s link speed.
Input Reference Clock Frequency
Selects the input frequency of the reference clock provided on sys_clk. It is the GT REFCLK frequency for the IP. Supported values are 100 MHz, 125 MHz, and 250 MHz. For important information about clocking, see Clocking.
Output User Clock Frequency
Selects the frequency of the output USERCLK that can be used by the PCIe MAC.
Table 1. User Clock Options with AMD PCIe MAC
Speed Lane User Clock (in MHz)

Gen1

x1 62.5, 125, 250
x2 62.5, 125, 250
x4 62.5, 125, 250
x8 62.5, 125, 250
x16 62.5, 125, 250

Gen2

x1 62.5, 125, 250
x2 62.5, 125, 250
x4 62.5, 125, 250
x8 62.5, 125, 250
x16 62.5, 125, 250

Gen3

x1 62.5, 125, 250
x2 62.5, 125, 250
x4 62.5, 125, 250
x8 62.5, 125, 250
x16 62.5, 125, 250, 500

Gen4

x1 125, 250
x2 125, 250
x4 125, 250
x8 125, 250, 500

Gen5

x1 250, 500
x2 250, 500
x4 250, 500
For important information about clocking the core, see Clocking.
Output Core Clock Frequency
Selects the frequency of the output coreclk that can be used by the PCIe MAC. Based on the link speed, link width selection 250 MHz and 500 MHz options are available. For important information about clocking the core, see Clocking.
PLL Type
Selects the PLL type for GTs used. For all speed PCIe PHY IP uses LCPLL as PLL TYPE. But TXPROGDIV CLOCK SOURCE uses RPLL internally.
Table 2. PLL Type
Link Speed PLL Type Description
2.5 GT/s LCPLL The default is LCPLL.
5.0 GT/s LCPLL The default is LCPLL.
8.0 GT/s LCPLL The default is LCPLL.
16.0 GT/s LCPLL The default is LCPLL.
  1. Gen1x1 and Gen2x1 configuration has option to choose RPLL and LCPLL.