Generating Example Design - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English

For generating the IP Core, see Designing with the Core.

Figure 1. Adding Versal Adaptive SoC PHY for PCI Express Core into IPI Design

Figure 2. Configuring pcie_phy_versal IP

After the IP is generated, right-click the IP to generate the example design as shown in subsequent figures:

Figure 3. Open IP Example Design

Figure 4. Example Design for Gen5x4