Miscellaneous Ports for AMD PCIe MAC - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English
Table 1. Misc Ports for AMD PCIe MAC
Name Width Direction Clock Domain Description
pcie_ltssm_state 6 input pclk PCIe Link Training and Status State Machine. Per-Link.
pcie_link_reach_target 1 input pclk Indicates the Reach Length Target of current link. Per-Link.
  • 1’b0: Short Reach
  • 1’b1: Long Reach
  1. Refer to Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331) for APB related signals.