Interface Ports RX Equalization Signals for Third-Party MAC - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

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Table 1. RX Equalization Signals for Gen3 and Above Rate
Name Width I/O Clock Domain Description
phy_rxeq_ctrl[1:0] 2 Input pclk RX equalization control. Must set back to 00b when rxeq_done = 1b detected. Gen3 and above rate only. Per-lane.
  • 00b: Idle
  • 01b: Reserved
  • 10b: RX EQ
  • 11b: RX EQ Bypass
phy_rxeq_preset 3 Input pclk Not used
phy_rxeq_txpreset[3:0] 4 Input pclk Link partner status for TX preset. Gen3 and above rate only. Per-lane.
phy_rxeq_preset_sel 1 Output pclk This output port serves indications as Coefficient or preset when rxeq_done = 1b. Gen3 and above rate only. Per-lane.
  • 0b: Coefficient
  • 1b: Preset
phy_rxeq_lffs 6 Input pclk Not used
phy_rxeq_lffs_sel 1 Output pclk It will be ‘1’ when phy_rxeq_ctrl is 2’10/2’b11.
phy_rxeq_new_txcoeff[17:0] 18 Output pclk This is presented to the link partner to request new TX coefficient or preset. Valid only when RXEQ_DONE is High. When indicating preset, only the lower four bits are valid. Gen3 and above rate only. Per-lane.
phy_rxeq_adapt_done 1 Output pclk RX equalization adaptation done. Single PCLK cycle done indicator for rxeq_control = 10b and 11b. If both rxeq_adapt_done and rxeq_done are High, then RX equalization is successfully done. If rxeq_adapt_done is Low and rxeq_done is High, then RX equalization must be requested again. Gen3 and above rate only. Per-lane.
phy_rxeq_done 1 Output pclk RX equalization done. Single pclk cycle done indicator for rxeq_control. Must set pipe_rxeq_control back to 00b when pipe_rxeq_done = High is detected. RX equalization must be re-initiated if rxeq_adapt_done is not High. Gen3 and above rate only. Per-lane.
dbg_phy_rxeq_fsm 3 Output pclk Tell RX EQ FSM state:

FSM_IDLE = 3’d0



FSM_ADAPT = 3’d3

FSM_DONE = 3’d4