Versal Adaptive SoC PHY for PCI Express Support - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English

The following table summarizes the recommended default features supported for different line rates:

Table 1. Default Features Supported
Features Gen1 Gen2 Gen3 Gen4
Line Rate 2.5 GT/s 5 GT/s 8 GT/s 16 GT/s
PCLK Frequency 125 MHz 250 MHz 250 MHz 500 MHz
2-Byte Data Width Yes Yes
4-Byte Data Width Yes Yes
8-Byte Data Width  
LPM/DFE Mode LPM LPM DFE 1 DFE 1
RX Elastic Buffer with Clock Correction Yes Yes Yes Yes
8b/10b Encoder and Decoder Yes Yes
128b/130b Encoder and Decoder Yes Yes
N_FTS 255 255 255 255
AMD Versalâ„¢ Device GT Support GTY GTY GTY GTY
  1. PLL TYPE is always LCPLL and TXPROGDIV CLOCK SOURCE is always RPLL.