Versal Adaptive SoC PHY for PCI Express - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English

The Versal™ Adaptive SoC PHY for PCI Express® IP Core internally does not instantiate the GTY transceiver like the AMD UltraScale™ or AMD UltraScale+™ PCIe PHY IP. GT Quad in Versal adaptive SoC is always external to the PCIe PHY IP. PCIe PHY IP in Vivado uses block automation or on opening the example design of the PCIe PHY IP, you can get an integrated design where PCIe PHY IP and GT Quad are connected with the required connections. Versal adaptive SoC GT Quad is highly configurable and tightly integrated with the programmable logic resources.

The Versal™ Adaptive SoC PHY for PCI Express® IP Core by default is configured to work with AMD PCIe MAC using phy_use_xilinx_mac attribute set to true. Setting phy_use_xilinx_mac to true, bypasses TX equalization and RX equalization modules as these are present in AMD PCIe wrappers. For using this core with third party MAC IP, you need to set phy_use_xilinx_mac attribute to false. Setting phy_use_xilinx_mac to false, includes TX equalization and RX equalization modules in the PHY wrapper.