PSCLK – Phase Shift Clock

UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

This input pin provides the source clock for the dynamic phase shift interface. All other inputs are synchronous to the positive edge of this clock. The pin can be driven by an IBUF, IBUFG, BUFG, or BUFGCE. There are no dedicated connections to this clock input.