UltraScale Architecture Clocking Resources User Guide (UG572) - UG572

Document ID: UG572
Release Date: 2023-02-01
Revision: 1.10.2 English

UltraScale Architecture Clocking Resources User Guide
Overview
Introduction to UltraScale Architecture
Clocking Overview
Clocking Architecture Overview
Clock Routing Resources Overview
CMT Overview
Clocking Differences from Previous FPGA Generations
Key Differences from 7 Series FPGAs
Clocking Resources
Overview
Global Clock Inputs
Byte Clock Inputs
Clock Buffers and Clock Routing
Clock Structure
Clock Buffers
BUFGCTRL Clock Buffer Primitives
BUFGCTRL
BUFGCE_1
BUFGMUX and BUFGMUX_1
BUFGMUX_CTRL
Additional BUFGCTRL Use Models
Asynchronous MUX Using BUFGCTRL
BUFGMUX_CTRL with a Clock Enable
BUFGCE Clock Buffers
BUFG Clock Buffer
BUFCE_LEAF Clock Buffer
BUFGCE_DIV
BUFG_GT and BUFG_GT_SYNC
BUFG_PS
Clock Management Tile
Overview
MMCMs
General Usage Description
MMCM Primitives
MMCME3_BASE or MMCME4_BASE Primitives
MMCME3_ADV and MMCME4_ADV Primitives
Clock Network Deskew
Frequency Synthesis Only Using Integer Divide
Frequency Synthesis Using Fractional Divide in the MMCM
Jitter Filter
Limitations
VCO Operating Range
Minimum and Maximum Input Frequencies
Duty Cycle Programmability
Phase Shift
Static Phase Shift Mode (MMCM and PLL)
Interpolated Fine Phase Shift in Fixed or Dynamic Mode in the MMCM
Dynamic Phase Shift Interface in the MMCM
MMCM Clock Divide Dynamic Change
MMCM Counter Cascading
MMCM Programming
Determine the Input Frequency
Determine the M and D Values
MMCM Ports
MMCM Port Descriptions
CLKIN1 – Primary Reference Clock Input
CLKIN2 – Secondary Clock Input
CLKFBIN – Feedback Clock Input
CLKFBOUT – Dedicated MMCM Feedback Output
CLKFBOUTB – Inverted CLKFBOUT
CLKINSEL – Clock Input Select
RST – Asynchronous Reset Signal
PWRDWN – Power Down
DADDR[6:0] – Dynamic Reconfiguration Address
DI[15:0] – Dynamic Reconfiguration Data Input
DWE – Dynamic Reconfiguration Write Enable
DEN – Dynamic Reconfiguration Enable Strobe
DCLK – Dynamic Reconfiguration Reference Clock
PSCLK – Phase Shift Clock
PSEN – Phase Shift Enable
PSINCDEC – Phase Shift Increment/Decrement Control
CLKOUT[0:6] – Output Clocks
CLKOUT[0:3]B – Inverted Output Clocks
CLKINSTOPPED – Input Clock Status
CLKFBSTOPPED – Feedback Clock Status
LOCKED
DO[15:0] – Dynamic Reconfiguration Output Bus
DRDY – Dynamic Reconfiguration Ready
PSDONE – Phase Shift Done
CDDCREQ – Request a Clock Output Divide Change
CDDCDONE – Clock Output Change Done
MMCM Attributes
MMCM Clock Input Signals
Counter Control
Detailed VCO and Output Counter Waveforms
Reference Clock Switching
Missing Input Clock or Feedback Clock
MMCM Use Models
Clock Network Deskew
MMCM with Internal Feedback
Zero Delay Buffer
CMT to CMT Connection
Spread-Spectrum Clock Generation
MMCM Application Example
PLLs
General Usage Description
PLL Primitives
PLLE3_BASE and PLLE4_BASE Primitive
PLLE3_ADV and PLLE4_ADV Primitive
PLL Ports
PLL Port Descriptions
CLKIN – Reference Clock Input
RST – Asynchronous Reset Signal
PWRDWN – Power Down
CLKOUT[0:1] – Output Clocks
CLKFBOUT – Dedicated PLL Feedback Output
CLKFBIN – Feedback Clock Input
CLKOUTPHY – PHY Clock Output
CLKOUTPHYEN – PHY Clock Enable
CLKOUT[0:1]B – Inverted Output Clocks
LOCKED
DADDR[6:0] – Dynamic Reconfiguration Address
DI[15:0] – Dynamic Reconfiguration Data Input
DWE – Dynamic Reconfiguration Write Enable
DEN – Dynamic Reconfiguration Enable Strobe
DCLK – Dynamic Reconfiguration Reference Clock
DO[15:0] – Dynamic Reconfiguration Output Bus
DRDY – Dynamic Reconfiguration Ready
PLL Attributes
Dynamic Reconfiguration Port
Writing to the DRP Port
Reading from the DRP Port
Read—Write Operation
DRP Register Set
MMCM Registers
Example 1
Example 2
PLL Registers
VHDL and Verilog Templates and the Clocking Wizard
Clocking Guidelines
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
References
Please Read: Important Legal Notices
Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
References
Please Read: Important Legal Notices

Back to home page