DADDR[6:0] – Dynamic Reconfiguration Address

UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. The address value on this bus specifies the 16 configuration bits that are written or read with the next DCLK cycle. When not used, all bits must be assigned zeros.