PLLE3_BASE and PLLE4_BASE Primitive

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID
UG572
Release Date
2023-02-01
Revision
1.10.2 English

The PLLE#_BASE primitive provides access to the most frequently used features of a stand-alone PLL. Clock deskew, frequency synthesis, and duty cycle programming are available to use with the PLLE#_BASE. The ports are listed in Table: PLLE#_BASE Ports .

Table 3-9: PLLE#_BASE Ports

Description

Ports

Clock input

CLKIN, CLKFBIN

Control inputs

RST, CLKOUTPHYEN

Clock output

CLKOUT0, CLKOUT1, CLKOUT0B, CLKOUT1B, CLKOUTPHY, CLKFBOUT

Status and data outputs

LOCKED

Power control

PWRDWN