UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

This output from the PLL is used to indicate when the PLLs have achieved frequency alignment of the reference clock and the internal feedback. Frequency alignment is within a predefined window of frequency matching within a predefined PPM range. The PLL automatically locks after power on; no extra reset is required. LOCKED is deasserted within one PFD clock cycle if the input clock stops or the frequency has changed. The PLL must be reset when LOCKED is deasserted. The clock outputs should not be used prior to the assertion of LOCKED.