MMCM Attributes - UG572

UltraScale Architecture Clocking Resources User Guide (UG572)
Document ID
UG572
Release Date
2025-05-29
Revision
1.11 English

The following table lists the attributes for the MMCME#_BASE and MMCME#_ADV primitives.

Table 1. MMCM Attributes
Attribute Type Allowed Values Default Description
BANDWIDTH String

HIGH

LOW

OPTIMIZED 6

OPTIMIZED Specifies the MMCM programming algorithm affecting the jitter, phase margin, and other characteristics of the MMCM.
CLKOUT[1:6]_DIVIDE Integer 1 to 128 1 Specifies the amount to divide the associated CLKOUT clock output if a different frequency is desired. This number, in combination with the CLKFBOUT_MULT_F and DIVCLK_DIVIDE values, determines the output frequency.
CLKOUT[0]_DIVIDE_F 1

Integer or Real

1 to 128 or

2.000 to 128.000 in increments of 0.125

 1
CLKOUT[0:6]_PHASE Real

–360.000 to 360.000

See equations in the Static Phase Shift Mode (MMCM and PLL) section.

 0.0 Specifies the output phase relationship of the associated CLKOUT clock output in number of degrees offset (i.e., 90 indicates a 90° or ¼ cycle offset phase offset while 180 indicates a 180° offset or ½ cycle phase offset).
CLKOUT[0:6]_DUTY_CYCLE Real 0.01 to 0.99 0.50 Specifies the duty cycle of the associated CLKOUT clock output as a percentage (i.e., 0.50 generates a 50% duty cycle).
CLKFBOUT_MULT_F 1

Integer or Real

2 to 64 or

2.000 to 64.000 in increments of 0.125

 5 This CLKFBOUT_MULT_F range applies to UltraScale devices. Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, determines the output frequency.
CLKFBOUT_MULT_F 1

Integer or

Real

2 to 128 or

2.000 to 128.000 in increments of 0.125

 5 This CLKFBOUT_MULT_F range applies to UltraScale+ devices. Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, determines the output frequency.
DIVCLK_DIVIDE Integer 1 to 106 1 Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD.
CLKFBOUT_PHASE Real –360.000 to 360.000 0.0 Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the MMCM.

REF_JITTER1

REF_JITTER2

 Real 0.000 to 0.999 0.010 Allows specification of the expected jitter on the reference clock to better optimize MMCM performance. A bandwidth setting of OPTIMIZED attempts to choose the best parameter for input clocking when unknown. If known, the value provided should be specified in terms of the unit interval (UI) (the maximum peak-to-peak value) of the expected jitter on the input clock.
CLKIN1_PERIOD Real 0.968 to 100.000 0.000 Specifies the input period in ns to the MMCM CLKIN1 input. Resolution is down to the ps. This information is mandatory and must be supplied.
CLKIN2_PERIOD Real 0.968 to 100.000 0.000 Specifies the input period in ns to the MMCM CLKIN2 input. Resolution is down to the ps. This information is mandatory and must be supplied.
CLKFBOUT_USE_FINE_PS 2 String FALSE, TRUE FALSE CLKFBOUT counter variable fine phase shift enable.
CLKOUT0_USE_FINE_PS 2 String FALSE, TRUE FALSE CLKOUT0 counter variable fine phase shift enable. CLKOUT0_DIVIDE must be an integer. Therefore, fractional divide is not allowed.
CLKOUT[1:6]_USE_FINE_PS 2 String FALSE, TRUE FALSE CLKOUT[1:6] variable fine phase shift enable.
STARTUP_WAIT String FALSE, TRUE FALSE Wait during the configuration start-up cycle for the MMCM to lock.
CLKOUT4_CASCADE String FALSE, TRUE FALSE Cascades the output divider (counter) CLKOUT6 into the input of the CLKOUT4 divider for an output clock divider that is greater than 128, effectively providing a total divide value of 16,384.
COMPENSATION String

AUTO 3 , ZHOLD, EXTERNAL, INTERNAL 5 , BUF_IN

 AUTO

Clock input compensation. Must be set to AUTO. Defines how the MMCM feedback is configured.

ZHOLD: Indicates the MMCM is configured to provide a negative hold time at the I/O registers.

EXTERNAL: Indicates a network external to the device is being compensated.

INTERNAL: Indicates the MMCM is using its own internal feedback path so no delay is being compensated.

BUF_IN: Indicates that the configuration does not match with the other compensation modes. The CLKIN and CLKFBIN pins are aligned in a way that a delay in the feedback path is compensated with respect to CLKIN.
SS_EN String FALSE, TRUE FALSE Enables spread spectrum generation.
SS_MODE String

DOWN_LOW,

DOWN_HIGH,

CENTER_LOW,

CENTER_HIGH

CENTER_

HIGH

 Controls the spread spectrum frequency deviation and the spread type.
SS_MOD_PERIOD Integer 4000–40000 10000 Specifies the spread spectrum modulation period (ns).
  1. The Vivado tools round up or down to the nearest multiple of 0.125 during bitstream implementation if the value is not specified as an exact 1/8th fraction. However, the attribute must be specified to the nearest multiple of 0.125 in the Verilog or VHDL code for proper clock frequency calculation during timing analysis.
  2. When using the variable fine phase shift, the initial phase shift value is always zero and cannot be preset to a static, initial phase.
  3. The COMPENSATION attribute values are documented for informational purpose only. The Vivado tools automatically select the appropriate compensation based on circuit topology. Do not manually select a compensation value, leave the attribute at the default value.
  4. The specifications for the VCO frequencies MMCM_FVCOMIN/MMCM_FVCOMAX and minimum out frequency MMCM_FOUTMIN are different for the UltraScale and UltraScale+ families. Consult the appropriate data sheets.
  5. The direct source code connection (wire) from CLKFBOUT to CLKFBIN is optimized away during synthesis.
  6. When using an SEM-IP in UltraScale devices only, additional noise is coupled into VCO of MMCM and PLL. This results in higher TIE jitter value as described in Answer Record 71314. Refer to the answer record for guidance and mitigation techniques. To resolve the issue of TIE jitter for SEM-IP, there are two new configurable properties: BITSTREAM.MMCM.BANDWIDTH and BITSTREAM.PLL.BANDWIDTH. If the properties are set to POSTCRC, each MMCM instance that has the BANDWIDTH attribute set to OPTIMIZED, or to a PLL instance with an implicit BANDWIDTH=OPTIMIZED attribute, gets configured to POSTCTRC bandwidth settings. Refer to the Vivado Design Suite User Guide: Programming and Debugging (UG908) for BITSTREAM property information.