DCLK – Dynamic Reconfiguration Reference Clock

UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

DCLK is the reference clock for the dynamic reconfiguration port. The rising edge of this signal is the timing reference for all other port signals. The setup time is specified in the UltraScale device data sheets [Ref 5] . There is no hold time requirement for the other input signals relative to the rising edge of DCLK. This signal can be driven by an IBUF, IBUFG, BUFGCE, or BUFGCTRL. There are no dedicated connections to this clock input.