Clock Routing Resources Overview

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID
Release Date
1.10.2 English

Each I/O bank contains global clock input pins to bring user clocks onto the device clock management and routing resources. The global clock inputs bring user clocks onto:

Clock buffers in the PHY adjacent to the same bank

CMTs in the PHY adjacent to the same bank

Each device has three global clock buffers: BUFGCTRL, BUFGCE, and BUFGCE_DIV. In addition, there is a local BUFCE_LEAF clock buffer for driving leaf clocks from horizontal distribution to various blocks in the device. BUFGCTRL has derivative software representations of types BUFGMUX, BUFGMUX1, BUFGMUX_CTRL, and BUFGCE_1. BUFGCE is for glitchless clock gating and has software derivative BUFG (BUFGCE with clock enable tied High). The global clock buffers drive routing and distribution tracks into the device logic via HCS rows. There are 24 routing and 24 distribution tracks in each HCS row. There is also a BUFG_GT that generates divided clocks for GT clocking. The clock buffers:

Can be used as a clock enable circuit to enable or disable clocks either globally, locally, or within a CR for fine-grained power control.

Can be used as a glitch-free multiplexer to:

° select between two clock sources.

° switch away from a failed clock source.

Are often driven by a CMT to:

° eliminate the clock distribution delay.

° adjust clock delay relative to another clock.

Clocking Resources , has further details on global clocks, I/O, and GT clocking. It also describes which clock routing resources to utilize for various applications.