BUFGCE is a clock buffer with one clock input, one clock output, and a clock enable line ( This Figure ). This buffer provides glitchless clock gating. BUFGCE can directly drive the routing resources and is a clock buffer with a single gated input. Its O output is 0 when CE is Low (inactive). When CE is High, the I input is transferred to the O output.
Table: BUFGCE Pins lists the BUFGCE pins.
|
Pin Name |
Type |
Invertible |
Description |
|---|---|---|---|
|
CE |
Input |
TRUE |
Clock enable |
|
I |
Input |
FALSE |
Clock buffer |
|
O |
Output |
FALSE |
Clock buffer |
Table: BUFGCE Attributes shows the BUFGCE attributes.
This Figure shows the BUFGCE timing diagram.
