BUFGCE is a clock buffer with one clock input, one clock output, and a clock enable line (Figure 1). This buffer provides glitchless clock gating. BUFGCE can directly drive the routing resources and is a clock buffer with a single gated input. Its O output is 0 when CE is Low (inactive). When CE is High, the I input is transferred to the O output.
Figure 1. BUFGCE Buffer
The following table lists the BUFGCE pins.
| Pin Name | Type | Invertible | Description |
|---|---|---|---|
| CE | Input | TRUE | Clock enable |
| I | Input | FALSE | Clock buffer |
| O | Output | FALSE | Clock buffer |
The following table shows the BUFGCE attributes.
| Attribute Name | Values | Default | Type | Description |
|---|---|---|---|---|
| CE_TYPE | SYNC, ASYNC | SYNC | STRING | Sets the clock enable behavior where SYNC allows for glitchless transition while ASYNC allows immediate transition. |
The following figure shows the BUFGCE timing diagram.
Figure 2. BUFGCE Timing Diagram
