Asynchronous MUX Using BUFGCTRL

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID
Release Date
1.10.2 English

In some cases an application requires immediate switching between clock inputs or bypassing the edge sensitivity of BUFGCTRL. An example is when one of the clock inputs is no longer switching. If this happens, the clock output would not have the proper switching conditions because the BUFGCTRL never detected a clock edge. This case uses the asynchronous MUX. This Figure illustrates an asynchronous MUX with BUFGCTRL design example.

Figure 2-14: Asynchronous MUX with BUFGCTRL Design Example

X-Ref Target - Figure 2-14


This Figure shows the asynchronous MUX timing diagram.

Figure 2-15: Asynchronous MUX Timing Diagram

X-Ref Target - Figure 2-15


In This Figure :

The current clock is from I0.

S is activated High.

The clock output immediately switches to I1.

When ignore signals are asserted High, glitch protection is disabled.