Counter Control

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID
UG572
Release Date
2023-02-01
Revision
1.10.2 English

The MMCM output counters provide a wide variety of synthesized clocks using a combination of DIVIDE, DUTY_CYCLE, and PHASE. This Figure illustrates how the counter settings impact the counter output.

The top waveform represents the output from the VCO.

Figure 3-6: Output Counter Clock Synthesis Examples

X-Ref Target - Figure 3-6

X16687-output-counter-clk-synth-timing.jpg