PLLE3_ADV and PLLE4_ADV Primitive

UltraScale Architecture Clocking Resources User Guide (UG572)

Document ID

UG572

Release Date

2023-02-01

Revision

1.10.2 English

The PLLE#_ADV primitive provides access to all PLLE#_BASE features plus additional ports for access to the DRP. The ports are listed in Table: PLLE#_ADV Ports .

Table 3-10: PLLE#_ADV Ports
Description	Ports
Clock input	CLKIN, DCLK, CLKFBIN
Control and data input	RST, CLKOUTPHYEN, DWE, DEN, DADDR, DI
Clock output	CLKOUT0, CLKOUT1, CLKOUT0B, CLKOUT1B, CLKOUTPHY, CLKFBOUT
Status and data output	LOCKED, DO, DRDY
Power control	PWRDWN