Reading from the DRP Port

UltraScale Architecture Clocking Resources User Guide (UG572)

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1.10.2 English

1. Put the address of the register to read from on the DADDR[n:0] bus.

2. Leave the DWE signal Low at all times when reading.

3. The value ON/OFF of the DI[15:0] bus does not matter.

4. Pulse the DEN signal High for one clock cycle. The DEN signal is the trigger that makes the DRP port function. When this signal is captured on the rising edge of the clock the internals of the DRP port capture the address to make sure that the contents of the correct register in the DRP map are reflected on the DO[15:0] output.

5. The DRP ports pulse the DRDY High for a clock cycle to confirm that the provided data is written into the provided address space. This also signals that a new write or read operation can start.

Figure 3-21: Reading from the DRP Port

X-Ref Target - Figure 3-21