Termination Options

UltraScale Architecture SelectIO Resources User Guide (UG571)
Document ID
UG571
Release Date
2023-08-31
Revision
1.15 English

The Vivado® Design Suite can perform simultaneous switching noise (SSN) analysis for each design, taking into account the actual I/O standards and options assigned to the I/O pins in the target device and package.

For each output pin, there is the option to specify whether or not termination is present on the board. The off-chip termination field automatically populates with the default terminations for each I/O standard, if one exists.

Table: Default Terminations for SSN Noise Analysis by I/O Standard lists all of the default terminations for each of the I/O standards supported by UltraScale™ devices when using the SSN predictor tool within the Vivado Design Suite. For each I/O pin in the design, you can specify whether to use these terminations, or to have no termination.

Table A-1: Default Terminations for SSN Noise Analysis by I/O Standard

I/O Standard

Drive

Termination Option

BLVDS_25

–

Near Series 165 Ω , Near Differential 140 W, and Far Differential 100 Ω

DIFF_HSTL_I

–

Far V TT 40 Ω

DIFF_HSTL_I_12

–

Far V TT 40 Ω

DIFF_HSTL_I_DCI_12

–

Far V TT 40 Ω

DIFF_HSTL_I_18

–

Far V TT 50 Ω

DIFF_HSTL_I_DCI

–

Far V TT 40 Ω

DIFF_HSTL_I_DCI_18

–

Far V TT 50 Ω

DIFF_HSTL_II

–

Near V TT 50 Ω & Far V TT 50 Ω

DIFF_HSTL_II_18

–

Near V TT 50 Ω & Far V TT 50 Ω

DIFF_HSUL_12

–

None

DIFF_HSUL_12_DCI

–

None

DIFF_POD10

–

Far V CCO 40 Ω

DIFF_POD10_DCI

–

Far V CCO 40 Ω

DIFF_POD12

–

Far V CCO 40 Ω

DIFF_POD12_DCI

–

Far V CCO 40 Ω

DIFF_SSTL12

–

Far V TT 40 Ω

DIFF_SSTL12_DCI

–

Far V TT 40 Ω

DIFF_SSTL135

–

Far V TT 40 Ω

DIFF_SSTL135_DCI

–

Far V TT 40 Ω

DIFF_SSTL135_R

–

Far V TT 40 Ω

DIFF_SSTL15

–

Far V TT 40 Ω

DIFF_SSTL15_DCI

–

Far V TT 40 Ω

DIFF_SSTL15_R

–

Far V TT 50 Ω

DIFF_SSTL18_I

–

Far V TT 50 Ω

DIFF_SSTL18_I_DCI

–

Far V TT 50 Ω

DIFF_SSTL18_II

–

Near V TT 50 Ω & Far V TT 50 Ω

HSLVDCI_15

–

None

HSLVDCI_18

–

None

HSTL_I

–

Far V TT 40 Ω

HSTL_I_12

–

Far V TT 40 Ω

HSTL_I_DCI_12

–

Far V TT 40 Ω

HSTL_I_18

–

Far V TT 50 Ω

HSTL_I_DCI

–

Far V TT 40 Ω

HSTL_I_DCI_18

–

Far V TT 50 Ω

HSTL_II

–

Near V TT 50 Ω & Far V TT 50 Ω

HSTL_II_18

–

Near V TT 50 Ω & Far V TT 50 Ω

HSUL_12

–

None

HSUL_12_DCI

–

None

LVCMOS12

2

None

LVCMOS12

4

None

LVCMOS12

6

None

LVCMOS12

8

None

LVCMOS12

12

Far V TT 50 Ω

LVCMOS15

2

None

LVCMOS15

4

None

LVCMOS15

6

None

LVCMOS15

8

None

LVCMOS15

12

Far V TT 50 Ω

LVCMOS15

16

Far V TT 50 Ω

LVCMOS18

2

None

LVCMOS18

4

None

LVCMOS18

6

None

LVCMOS18

8

None

LVCMOS18

12

Far V TT 50 Ω

LVCMOS18

16

Far V TT 50 Ω

LVCMOS25

4

None

LVCMOS25

8

None

LVCMOS25

12

Far V TT 50 Ω

LVCMOS25

16

Far V TT 50 Ω

LVCMOS33

4

None

LVCMOS33

8

None

LVCMOS33

12

Far V TT 50 Ω

LVCMOS33

16

Far V TT 50 Ω

LVDCI_15

–

None

LVDCI_18

–

None

LVDS

–

Far Differential 100 Ω

LVDS_25

–

Far Differential 100 Ω

LVDS_25_PE

–

Far Differential 100 Ω

LVDS_PE

–

Far Differential 100 Ω

LVTTL

4

None

LVTTL

8

None

LVTTL

12

Far V TT 50 Ω

LVTTL

16

Far V TT 50 Ω

MINI_LVDS_25

–

Far Differential 100 Ω

POD10

–

Far V CCO 40 Ω

POD10_DCI

–

Far V CCO 40 Ω

POD12

–

Far V CCO 40 Ω

POD12_DCI

–

Far V CCO 40 Ω

PPDS_25

–

Far Differential 100 Ω

RSDS_25

–

Far Differential 100 Ω

SSTL12

–

Far V TT 40 Ω

SSTL12_DCI

–

Far V TT 40 Ω

SSTL135

–

Far V TT 40 Ω

SSTL135_DCI

–

Far V TT 40 Ω

SSTL135_R

–

Far V TT 40 Ω

SSTL15

–

Far V TT 40 Ω

SSTL15_DCI

–

Far V TT 40 Ω

SSTL15_R

–

Far V TT 50 Ω

SSTL18_I

–

Far V TT 50 Ω

SSTL18_I_DCI

–

Far V TT 50 Ω

SSTL18_II

–

Near V TT 50 Ω & Far V TT 50 Ω

TMDS_33

–

Far 3.3V 50 Ω

SUB_LVDS

–

Far Differential 100 Ω

This Figure illustrates each of these terminations.

Figure A-1: Default Terminations

X-Ref Target - Figure A-1

X17678-default-terminations.jpg