Differential HSUL

Differential HSUL_12

UltraScale Architecture SelectIO Resources User Guide (UG571)

Document ID

UG571

Release Date

2023-08-31

Revision

1.15 English

This Figure shows a sample circuit illustrating a board topology for differential HSUL_12 with unidirectional signaling.

Figure 1-73: Differential HSUL_12 with Unidirectional Signaling
X-Ref Target - Figure 1-73

This Figure shows a sample circuit illustrating a board topology for differential HSUL_12 with unidirectional DCI signaling.

Figure 1-74: Differential HSUL_12 with Unidirectional DCI Signaling
X-Ref Target - Figure 1-74

This Figure shows a sample circuit illustrating a board topology for differential HSUL_12 with bidirectional signaling.

Figure 1-75: Differential HSUL_12 with Bidirectional Signaling
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This Figure shows a sample circuit illustrating a board topology for differential HSUL_12 with bidirectional DCI signaling.

Figure 1-76: Differential HSUL_12 with DCI Bidirectional Signaling
X-Ref Target - Figure 1-76

Table: HSUL Allowed Attributes lists the allowed attributes for HSUL I/O standards. Support is implied for primitives that are derivatives of the primitives listed in Table: HSUL Allowed Attributes (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to the SelectIO Interface Primitives section for all supported derivatives.

Table 1-48: HSUL Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3				OBUF/OBUFT				IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	HP I/O		HR I/O		HP I/O		HR I/O		HP I/O		HR I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	HSUL_12 DIFF_HSUL_12		HSUL_12 DIFF_HSUL_12		HSUL_12 DIFF_HSUL_12		HSUL_12 DIFF_HSUL_12		HSUL_12 DIFF_HSUL_12		HSUL_12 DIFF_HSUL_12
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW	FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW
ODT	RTT_120 RTT_240 RTT_NONE	RTT_NONE	N/A		N/A		N/A		RTT_120 RTT_240 RTT_NONE	RTT_NONE	N/A
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A
IOSTANDARD	HSUL_12_DCI DIFF_HSUL_12_DCI		N/A		HSUL_12_DCI DIFF_HSUL_12_DCI		N/A		HSUL_12_DCI DIFF_HSUL_12_DCI		N/A
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	N/A		FAST MEDIUM SLOW	SLOW	N/A
DQS_BIAS ⁽¹⁾	TRUE FALSE	FALSE	N/A		N/A		N/A		TRUE FALSE	FALSE	N/A
ODT	RTT_120 RTT_240 RTT_NONE	RTT_NONE	N/A		N/A		N/A		RTT_120 RTT_240 RTT_NONE	RTT_NONE	N/A
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_48_48	N/A
Notes: 1. Applies to DIFF_HSUL12 I/O standards.