Table: IDELAYCTRL Ports
lists the IDELAYCTRL ports.
Table 2-17:
IDELAYCTRL Ports
|
Port
|
I/O
|
Type
|
Description
|
|
REFCLK
|
Input
|
Clock
|
Reference clock for delay calibration.
|
|
RST
|
Input
|
Reset
|
Active-High asynchronous reset for IDELAYCTRL.
Note:
The reset for all used IDELAYCTRLs/BITSLICE_CONTROLs within a bank must be released at the same time due to the cascaded DLY_RDY connections between the BITSLICE_CONTROLs. Failure to do so might result in DLY_RDY for one of the IDELAYCTRLs/BITSLICE_CONTROLs not asserting.
|
|
RDY
|
Output
|
Data
|
The ready signal goes High to signal that controlled IDELAYE3 and ODELAYE3 primitives are calibrated.
|
Table 2-18:
IDELAYCTRL Attribute
|
Attribute
|
Values
|
Default
|
Type
|
Description
|
|
SIM_DEVICE
|
7SERIES, ULTRASCALE
|
ULTRASCALE
|
String
|
Set to ULTRASCALE for UltraScale and UltraScale+ devices.
|