The SelectIO pins can be configured to various I/O standards.
• Single-ended I/O standards (LVTTL and LVCMOS)
• Voltage-referenced I/O standards (SSTL, HSTL, and HSUL)
• Pseudo-differential I/O standards (differential SSTL and differential HSTL)
• True-differential inputs (LVDS, LVPECL)
Table: HD I/O Supported Standards lists the HD I/O supported standards with their respective features.
I/O Standard |
Driver Features |
Receiver Features |
|
---|---|---|---|
DRIVE |
SLEW |
ODT |
|
4, 8, 12 |
SLOW, FAST |
– |
|
4, 8, 12, 16 |
SLOW, FAST |
– |
|
4, 8, 12, 16 |
SLOW, FAST |
– |
|
4, 8, 12, 16 |
SLOW, FAST |
– |
|
4, 8, 12, 16 |
SLOW, FAST |
– |
|
4, 8, 12, 16 |
SLOW, FAST |
– |
|
HSUL_12 (1) |
– |
SLOW, FAST |
– |
HSTL_I (1) |
– |
SLOW, FAST |
RTT_48 |
HSTL_I_18 (1) |
– |
SLOW, FAST |
RTT_48 |
SSTL18_I (1) |
– |
SLOW, FAST |
RTT_48 |
SSTL18_II (1) |
– |
SLOW, FAST |
RTT_48 |
SSTL15 (1) |
– |
SLOW, FAST |
RTT_48 |
SSTL15_II (1) |
– |
SLOW, FAST |
RTT_48 |
SSTL135 (1) |
– |
SLOW, FAST |
RTT_48 |
SSTL135_II (1) |
– |
SLOW, FAST |
RTT_48 |
SSTL12 (1) |
– |
SLOW, FAST |
RTT_48 |
DIFF_HSTL_I (1) |
– |
SLOW, FAST |
RTT_48 |
DIFF_HSTL_I_18 (1) |
– |
SLOW, FAST |
RTT_48 |
DIFF_SSTL18_I (1) |
– |
SLOW, FAST |
RTT_48 |
DIFF_SSTL18_II (1) |
– |
SLOW, FAST |
RTT_48 |
DIFF_SSTL15 (1) |
– |
SLOW, FAST |
RTT_48 |
DIFF_SSTL15_II (1) |
– |
SLOW, FAST |
RTT_48 |
DIFF_SSTL135 (1) |
– |
SLOW, FAST |
RTT_48 |
DIFF_SSTL135_II (1) |
– |
SLOW, FAST |
RTT_48 |
DIFF_SSTL12 (1) |
– |
SLOW, FAST |
RTT_48 |
DIFF_HSUL_12 |
– |
SLOW, FAST |
– |
LVPECL (receiver only) (1) |
N/A |
N/A |
– |
N/A |
N/A |
– |
|
SUB_LVDS (receiver only) (1) |
N/A |
N/A |
– |
SLVS_400_25 (receiver only) (1) |
N/A |
N/A |
– |
Notes: 1. Maximum frequency of operation is 250 Mb/s DDR. 2. For 4 mA drive strength, the maximum frequency of operation is limited to 125 Mb/s. 3. There is not a specific requirement on the V CCO bank voltage on LVDS_25 inputs provided the V CCO level is high enough to ensure the pin voltage aligns to the V in spec in the Recommended Operating Conditions table of the specific UltraScale+ device data sheet [Ref 2] . |