HD I/O Supported Standards

LVCMOS12 ^{(1) (2)}

4, 8, 12

SLOW, FAST

–

LVCMOS15 ^{(1) (2)}

4, 8, 12, 16

SLOW, FAST

–

LVCMOS18 ^{(1) (2)}

4, 8, 12, 16

SLOW, FAST

–

LVCMOS25 ^{(1) (2)}

4, 8, 12, 16

SLOW, FAST

–

LVCMOS33 ^{(1) (2)}

4, 8, 12, 16

SLOW, FAST

–

LVTTL ^{(1) (2)}

4, 8, 12, 16

SLOW, FAST

–

HSUL_12 ⁽¹⁾

–

SLOW, FAST

–

HSTL_I ⁽¹⁾

–

SLOW, FAST

RTT_48

HSTL_I_18 ⁽¹⁾

–

SLOW, FAST

RTT_48

SSTL18_I ⁽¹⁾

–

SLOW, FAST

RTT_48

SSTL18_II ⁽¹⁾

–

SLOW, FAST

RTT_48

SSTL15 ⁽¹⁾

–

SLOW, FAST

RTT_48

SSTL15_II ⁽¹⁾

–

SLOW, FAST

RTT_48

SSTL135 ⁽¹⁾

–

SLOW, FAST

RTT_48

SSTL135_II ⁽¹⁾

–

SLOW, FAST

RTT_48

SSTL12 ⁽¹⁾

–

SLOW, FAST

RTT_48

DIFF_HSTL_I ⁽¹⁾

–

SLOW, FAST

RTT_48

DIFF_HSTL_I_18 ⁽¹⁾

–

SLOW, FAST

RTT_48

DIFF_SSTL18_I ⁽¹⁾

–

SLOW, FAST

RTT_48

DIFF_SSTL18_II ⁽¹⁾

–

SLOW, FAST

RTT_48

DIFF_SSTL15 ⁽¹⁾

–

SLOW, FAST

RTT_48

DIFF_SSTL15_II ⁽¹⁾

–

SLOW, FAST

RTT_48

DIFF_SSTL135 ⁽¹⁾

–

SLOW, FAST

RTT_48

DIFF_SSTL135_II ⁽¹⁾

–

SLOW, FAST

RTT_48

DIFF_SSTL12 ⁽¹⁾

–

SLOW, FAST

RTT_48

DIFF_HSUL_12

–

SLOW, FAST

–

LVPECL (receiver only) ⁽¹⁾

N/A

N/A

–

LVDS_25 (receiver only) ^{(1) (3)}

N/A

N/A

–

SUB_LVDS (receiver only) ⁽¹⁾

N/A

N/A

–

SLVS_400_25 (receiver only) ⁽¹⁾

N/A

N/A

–

Notes:

1. Maximum frequency of operation is 250 Mb/s DDR.

2. For 4 mA drive strength, the maximum frequency of operation is limited to 125 Mb/s.

3. There is not a specific requirement on the V _CCO bank voltage on LVDS_25 inputs provided the V _CCO level is high enough to ensure the pin voltage aligns to the V _in spec in the Recommended Operating Conditions table of the specific UltraScale+ device data sheet [Ref 2] .