This Figure is an example of differential termination for an LVDS or LVDS_25 receiver on a board with 50 Ω transmission lines.
This Figure is an example of internal differential termination for an LVDS or LVDS_25 receiver on a board with 50 Ω transmission lines.
Table: Allowed Attributes for the LVDS I/O Standards lists the allowed attributes for the LVDS I/O standards. Support is implied for primitives that are derivatives of the primitives listed in Table: Allowed Attributes for the LVDS I/O Standards (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to the SelectIO Interface Primitives section for all supported derivatives.
Attributes |
IBUFDS |
OBUFDS |
||||||
---|---|---|---|---|---|---|---|---|
HP I/O |
HR I/O |
HP I/O |
HR I/O |
|||||
Allowed Values |
Default |
Allowed Values |
Default |
Allowed Values |
Default |
Allowed Values |
Default |
|
IOSTANDARD |
LVDS |
LVDS_25 |
LVDS |
LVDS_25 |
||||
DQS_BIAS (1) |
FALSE |
N/A |
N/A |
N/A |
||||
EQUALIZATION |
EQ_LEVEL0
|
EQ_NONE |
EQ_LEVEL0
|
EQ_NONE |
N/A |
N/A |
||
LVDS_PRE_EMPHASIS (6) |
N/A |
N/A |
TRUE (4) FALSE |
FALSE |
TRUE (4) FALSE |
FALSE |
||
DIFF_TERM |
TRUE
|
FALSE |
TRUE
|
FALSE |
N/A |
N/A |
||
DIFF_TERM_ADV |
TERM_100
|
TERM_NONE |
TERM_100
|
TERM_NONE |
N/A |
N/A |
||
Notes: 1. The DQS_BIAS attribute is set on the I/O port rather than the primitive. 2. The allowed combinations of DQS_BIAS and EQUALIZATION are listed in Table: Allowed Combinations of DQS_BIAS and EQUALIZATION (HP I/O Banks) . 3. DQS_BIAS = TRUE is only allowed in AC coupled applications to provide a bias level to V CCO /2 on both P and N sides of the input pin. 4. LVDS_PRE_EMPHASIS = TRUE is only supported in AC coupled applications. 5. Allowed values of equalization for AC coupled and DC coupled interface are listed in Table: HR I/O Bank Equalization . 6. This attribute must be used in conjunction with ENABLE_PRE_EMPHASIS to enable the pre-emphasis function. |
It is acceptable to have differential inputs such as LVDS and LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those standards (1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs). However, these criteria must be met:
• The optional internal differential termination is not used.
° DIFF_TERM_ADV = TERM_NONE
° DIFF_TERM = FALSE (default).
• The differential signals at the input pins meet the V IN requirements in the Recommended Operating Conditions table of the specific UltraScale device data sheet [Ref 2] .
• The differential signals at the input pins meet the V IDIFF (min) requirements in the corresponding LVDS or LVDS_25 DC specifications tables of the specific UltraScale device data sheet [Ref 2] .
One way to accomplish this criteria is to use an external circuit that both AC-couples and DC-biases the input signals. This Figure shows an example circuit for providing an AC-coupled and DC-biased circuit for a differential clock input. R DIFF provides the 100 Ω differential receiver termination because the internal DIFF_TERM_ADV = TERM_NONE or DIFF_TERM = FALSE. To maximize the input noise margin, all R BIAS resistors should be the same value, essentially creating a V ICM level of V BIAS /2. V BIAS should be a 1.8V source (typically V CCO or V CCAUX ) to ensure the input common-mode voltage for AC-coupled signals is maintained. Resistors in the 1K–100K Ω range are recommended. The typical values for the AC coupling capacitors C AC are in the range of 100 nF. All components should be placed physically close to the device inputs. See the specific UltraScale device data sheets [Ref 2] for the range of the bias voltage to be used with the receiver with and without equalization. Although the AC coupling mentioned in this section is intended for LVDS signaling, there are many alternate ways to provide bias and termination. For example, IOSTANDARDS like DIFF_SSTL and DCI split termination can often be used to provide both internal termination and bias to an AC-coupled signal at the cost of higher current draw through the termination network.
In UltraScale device HP I/O banks, there is an option to use internal bias voltage (DQS_BIAS) in AC-coupled LVDS applications. In such a configuration, EQUALIZATION must be set to EQ_LEVEL0 (1, 2, 3, or 4) for the correct operation, even though EQ_LEVEL0 does not provide equalization. When designing with Vivado Design Suite, the simulation behavior of the DQS_BIAS feature is not modeled when DQS_BIAS is used for DC biasing with an AC-coupled LVDS standard. When an input is 3-stated and the DQS_BIAS is set to TRUE for an LVDS input, the input to the general interconnect is an X in the hardware. Simulation models this condition as an input of 0 to the general interconnect.
In HR I/O banks there is an option to use internal bias voltage in AC-coupled LVDS applications by setting the attribute value, EQUALIZATION = EQ_LEVEL0_DC_BIAS (when EQUALIZATION is not required) or EQ_LEVEL1/2/3/4_DC_BIAS. In DC-coupled applications, EQUALIZATION must be set to EQ_NONE.