Table: BITSLICE_CONTROL Ports and Attributes for the BISC Process
highlights the BITSLICE_CONTROL ports and attributes involved in the BISC process.
Table 2-35:
BITSLICE_CONTROL Ports and Attributes for the BISC Process
|
Pins
|
I/O
|
Type
|
Description
|
|
Logic Control
|
|
EN_VTC
|
In
|
Data
|
Enable VT tracking.
|
|
Status
|
|
VTC_RDY
|
Out
|
Data
|
Nibble ready for VT calibration
|
|
DLY_RDY
|
Out
|
Data
|
Nibble delay line calibration is complete.
|
|
RIU
|
|
RIU_CLK
|
In
|
Clock
|
Clock from interconnect logic. The RIU clock must be connected in for the BISC process to complete.
|
|
RIU_ADDR[5:0]
|
In
|
Data
|
Register address.
|
|
RIU_WR_DATA[15:0]
|
In
|
Data
|
Data write to register.
|
|
RIU_RD_DATA[15:0]
|
Out
|
Data
|
Data read from register.
|
|
RIU_VALID
|
Out
|
Data
|
Status indicating if BISC is accessing RIU registers.
|
|
RIU_WR_EN
|
In
|
Enable
|
Register write enable (active-High).
|
|
RIU_NIBBLE_SEL
|
In
|
Data
|
Nibble in byte select. This signal must be High to perform read/write to the nibble.
|
|
Attributes
|
|
IDLY_VT_TRACK
|
|
|
Enable input delay line VT tracking.
|
|
ODLY_VT_TRACK
|
|
|
Enable output delay line VT tracking.
|
|
QDLY_VT_TRACK
|
|
|
Enable slave quarter delay VT tracking.
|
|
ROUNDING_FACTOR
|
|
|
Value to scale the VT tracking. This attribute has a default value that normally does not need to be changed.
|
|
SELF_CALIBRATE
|
|
|
Start a self-calibrate cycle.
|
|
RIU Registers
|
|
|
Read the RIU paragraph.
|