In SAME_EDGE mode, the data is presented into the device logic on the same clock edge. This Figure shows the timing diagram of the input DDR using the SAME_EDGE mode. In the timing diagram, the output pairs Q1 and Q2 are no longer (0) and (1). Instead, the first pair presented is pair Q1 (0) and Q2 (don’t care), followed by pair (1) and (2) on the next clock cycle.
