The SDR input and output registers use different resources than IDDR/ODDR registers and thus have different performance characteristics. SDR input and output registering inside the bit slice is performed using a flip-flop primitive in conjunction with the IOB = TRUE constraint applied to the flip-flop instance. Note that IS_D_INVERTED is not supported for UltraScale and UltraScale+ and must be set to 0. Simulation results do not match hardware if IS_D_INVERTED is set to 1. This can either be instantiated directly or is inferred by synthesis. Applicable elements are;
• FDCE, flip-flip with clock enable and asynchronous clear
• FDPE, flip-flop with clock enable and asynchronous preset
• FDRE, flip-flop with clock enable and synchronous reset
• FDSE, flip-flop with clock enable and synchronous set