Differential SSTL18, SSTL15, SSTL135, SSTL12

This Figure shows a sample circuit illustrating a termination technique for differential SSTL18, SSTL15, SSTL135, or SSTL12 with unidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (i.e., DIFF_SSTL12 should only interface with DIFF_SSTL12).

Figure 1-67: Differential SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional Termination
X-Ref Target - Figure 1-67

This Figure shows a sample circuit illustrating a termination technique for differential SSTL18, SSTL15, SSTL135, or SSTL12 with unidirectional DCI termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (i.e., DIFF_SSTL12_DCI should only interface with DIFF_SSTL12_DCI).

Figure 1-68: Differential SSTL18, SSTL15, SSTL135, or SSTL12 Unidirectional DCI Termination
X-Ref Target - Figure 1-68

This Figure shows a sample circuit illustrating a termination technique for differential SSTL18, SSTL15, SSTL135, or SSTL12 with bidirectional termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (i.e., DIFF_SSTL12 should only interface with DIFF_SSTL12).

Figure 1-69: Differential SSTL18, SSTL15, SSTL135, or SSTL12 with Bidirectional Termination
X-Ref Target - Figure 1-69

This Figure shows a sample circuit illustrating a termination technique for differential SSTL18, SSTL15, SSTL135, or SSTL12 with bidirectional DCI termination. In a specific circuit, all drivers and receivers must be at the same voltage level (1.8V, 1.5V, 1.35V, or 1.2V); they are not interchangeable (i.e., DIFF_SSTL12_DCI should only interface with DIFF_SSTL12_DCI). DCI standards are supported only in HP I/Os.

Figure 1-70: Differential SSTL18, SSTL15, SSTL135, or SSTL12 with Bidirectional DCI Termination
X-Ref Target - Figure 1-70

Table: SSTL Allowed Attributes lists the allowed attributes for SSTL I/O standards. Support is implied for primitives that are derivatives of the primitives listed in Table: SSTL Allowed Attributes (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to the SelectIO Interface Primitives section for all supported derivatives.

Table 1-44: SSTL Allowed Attributes
Attributes	IBUF/IBUFE3/IBUFDS/IBUFDSE3				OBUF/OBUFT				IOBUF/IOBUFE3/IOBUFDS/IOBUFDSE3
	HP I/O		HR I/O		HP I/O		HR I/O		HP I/O		HR I/O
	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default	Allowed Values	Default
IOSTANDARD	SSTL12 SSTL135 SSTL15 SSTL18_I		SSTL12 SSTL135 SSTL135_R SSTL15 SSTL15_R SSTL18_I		SSTL12 SSTL135 SSTL15 SSTL18_I		SSTL12 SSTL135 SSTL135_R SSTL15 SSTL15_R SSTL18_I		SSTL12 SSTL135 SSTL15 SSTL18_I		SSTL12 SSTL135 SSTL135_R SSTL15 SSTL15_R SSTL18_I
SLEW	N/A		N/A		FAST, MEDIUM, SLOW	SLOW	FAST SLOW	SLOW	FAST, MEDIUM, SLOW	SLOW	FAST SLOW	SLOW
ODT	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE	N/A		N/A		RTT_40 RTT_48 RTT_60 RTT_NONE ⁽¹⁾	RTT_NONE	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_40_40	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60 ⁽¹⁾	RDRV_40_40	N/A
IOSTANDARD	SSTL12_DCI SSTL135_DCI SSTL15_DCI SSTL18_I_DCI		N/A		SSTL12_DCI SSTL135_DCI SSTL15_DCI SSTL18_I_DCI		N/A		SSTL12_DCI SSTL135_DCI SSTL15_DCI SSTL18_I_DCI		N/A
SLEW	N/A		N/A		FAST, MEDIUM, SLOW	SLOW	N/A		FAST, MEDIUM, SLOW	SLOW	N/A
ODT	RTT_40 RTT_48 RTT_60	RTT_40	N/A		N/A		N/A		RTT_40 RTT_48 RTT_60 ⁽¹⁾ ⁽³⁾	RTT_40	N/A
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_40_40	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60 ⁽¹⁾	RDRV_40_40	N/A
IOSTANDARD	DIFF_SSTL12 DIFF_SSTL135 DIFF_SSTL15 DIFF_SSTL18_I		DIFF_SSTL12 DIFF_SSTL135 DIFF_SSTL15 DIFF_SSTL18_I		DIFF_SSTL12 DIFF_SSTL135 DIFF_SSTL15 DIFF_SSTL18_I		DIFF_SSTL12 DIFF_SSTL135 DIFF_SSTL15 DIFF_SSTL18_I		DIFF_SSTL12 DIFF_SSTL135 DIFF_SSTL15 DIFF_SSTL18_I		DIFF_SSTL12 DIFF_SSTL135 DIFF_SSTL15 DIFF_SSTL18_I
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW	FAST MEDIUM SLOW	SLOW	FAST SLOW	SLOW
DQS_BIAS ⁽²⁾	TRUE FALSE	FALSE	TRUE FALSE	FALSE	N/A		N/A		TRUE FALSE	FALSE	TRUE FALSE	FALSE
ODT	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE	N/A		N/A		RTT_40 RTT_48 RTT_60 RTT_NONE ⁽¹⁾	RTT_NONE	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_40_40	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60 ⁽¹⁾	RDRV_40_40	N/A
IOSTANDARD	DIFF_SSTL12_DCI DIFF_SSTL135_DCI DIFF_SSTL15_DCI DIFF_SSTL18_I_DCI		N/A		DIFF_SSTL12_DCI DIFF_SSTL135_DCI DIFF_SSTL15_DCI DIFF_SSTL18_I_DCI		N/A		DIFF_SSTL12_DCI DIFF_SSTL135_DCI DIFF_SSTL15_DCI DIFF_SSTL18_I_DCI		N/A
SLEW	N/A		N/A		FAST MEDIUM SLOW	SLOW	N/A		FAST MEDIUM SLOW	SLOW	N/A
DQS_BIAS ⁽²⁾ ⁽⁴⁾	TRUE FALSE	FALSE	N/A		N/A		N/A		TRUE FALSE	FALSE	N/A
ODT	RTT_40 RTT_48 RTT_60 ⁽³⁾	RTT_40	N/A		N/A		N/A		RTT_40 RTT_48 RTT_60 ⁽¹⁾ ⁽³⁾	RTT_40	N/A
OUTPUT_ IMPEDANCE	N/A		N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60	RDRV_40_40	N/A		RDRV_40_40 RDRV_48_48 RDRV_60_60 ⁽¹⁾	RDRV_40_40	N/A
IOSTANDARD	N/A		DIFF_SSTL135_R DIFF_SSTL15_R		N/A		DIFF_SSTL135_R DIFF_SSTL15_R		N/A		DIFF_SSTL135_R DIFF_SSTL15_R
SLEW	N/A		N/A		N/A		FAST SLOW	SLOW	N/A		FAST SLOW	SLOW
ODT	N/A		RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE	N/A		N/A		N/A		RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE
Notes: 1. The allowed bidirectional configuration combinations for driver output impedance (OUTPUT_IMPEDANCE) and ODT are listed in Table: Only Allowed Combinations for Bidirectional Configurations . 2. The DQS_BIAS attribute is set on the I/O port rather than the primitive. 3. ODT = RTT_NONE is not a valid setting for DCI I/O standards. 4. This is read-only on the primitive.

Table: SSTL Class II Allowed Attributes lists the allowed attributes for SSTL Class II I/O standards. Support is implied for primitives that are derivatives of the primitives listed in Table: SSTL Class II Allowed Attributes (for example: *_DIFF_OUT, *_DCIEN, *_IBUFDISABLE, or *_INTERMDISABLE). Refer to the SelectIO Interface Primitives section for all supported derivatives.

Table 1-45: SSTL Class II Allowed Attributes
Attributes	IBUF/IBUFDS			OBUF/OBUFT			IOBUF/IOBUFDS
	HP I/O	HR I/O		HP I/O	HR I/O		HP I/O	HR I/O
	HP I/O	Allowed Values	Default	HP I/O	Allowed Values	Default	HP I/O	Allowed Values	Default
IOSTANDARD	N/A	SSTL18_II DIFF_SSTL18_II		N/A	SSTL18_II DIFF_SSTL18_II		N/A	SSTL18_II DIFF_SSTL18_II
SLEW	N/A	N/A		N/A	FAST SLOW	SLOW	N/A	FAST SLOW	SLOW
ODT	N/A	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE	N/A	N/A		N/A	RTT_40 RTT_48 RTT_60 RTT_NONE	RTT_NONE