Table: ISERDESE3 Attributes
lists the ISERDESE3 attributes.
Table 2-7:
ISERDESE3 Attributes
|
Attribute
|
Values
|
Default
|
Type
|
Description
|
|
DATA_WIDTH
|
4 or 8
|
8
|
Decimal
|
Defines the serial-to-parallel converter width.
|
|
FIFO_ENABLE
|
TRUE/FALSE
|
FALSE
|
String
|
The FIFO is used when the attribute is set TRUE and bypassed when the attribute is set FALSE.
|
|
FIFO_SYNC_MODE
|
TRUE/FALSE
|
FALSE
|
String
|
Set to FALSE when the ISERDES internal FIFO write clock and the FIFO read clock accessed from FPGA logic are from separate or common clock domains. This is the preferred selection because it supports all clocking options.
TRUE: Reserved for later use.
|
|
IS_CLK_INVERTED
|
1 or 0
|
0
|
Bit
|
Sets a local clock inversion for CLK input.
|
|
IS_CLK_B_INVERTED
|
1 or 0
|
0
|
Bit
|
Sets a local clock inversion for CLK_B input. When IS_CLK_B_INVERTED=1, CLK and CLK_B must be driven by the same global clock buffer. When IS_CLK_B_INVERTED=0, CLK_B must be driven by the same global clock buffer as CLK through an inverter.
|
|
IS_RST_INVERTED
|
1 or 0
|
0
|
Bit
|
Sets a local inversion for RST input when 1.
|
|
SIM_DEVICE
|
ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2
|
ULTRASCALE
|
String
|
Device family for behavioral simulation
|