Delay Line Cascading

UltraScale Architecture SelectIO Resources User Guide (UG571)

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1.15 English

A feature not available in the RXTX_BITSLICE but available in the RX_BITSLICE is called cascade . This feature allows unused output delay lines in TX_BITSLICE cascaded to input delay lines in RX_BITSLICEs. The result is a delay line of double length passing data to the RX_BITSLICE deserializer registers. A single delay line is 512 taps. Cascading both input and output delay lines can double the length of the available delay. This feature is discussed in detail in the RX_BITSLICE Extended Delay Control Signals .