Clocking in Native Mode

BITSLICE_CONTROL Pins

PLL_CLK

Input

High-speed clock delivered by a PLL (CLKOUTPHY) in the same I/O bank and routed over dedicated resources. Normally, this clock is the same frequency as the required data rate (example: 1 GHz clock for a 1 Gb/s data rate). For designs using SERIAL mode, this clock is the serial DDR data sampling clock and thus equal to ½ the data rate (for example, for 1 Gb/s data rate, the DDR clock is 500 MHz).

REFCLK

Input

Clock delivered by an MMCM or PLL, not necessarily in the same I/O bank as the one using the BITSLICE_CONTROL components. This clock arrives at the BITSLICE_CONTROL over normal clock routing of the FPGA and uses BUFG and BUFGCE clock buffers.

• The PLL_CLK or REFCLK are referred to as the BITSLICE_CONTROL master clock.

• This master clock is selected by the REFCLK_SRC attribute.

• The clock source, PLL_CLK or REFCLK, is mutually exclusive (one or the other but not both).

CLK_FROM_EXT

Input

This input is part of the inter-byte clocking structure.

It is a clock routed over dedicated routing in the BITSLICE_CONTROL BITSLICE structure and comes from the CLK_TO_EXT_NORTH or CLK_TO_EXT_SOUTH outputs of a BITSLICE_CONTROL in a neighboring byte.

When not used, tie High.

CLK_TO_EXT_NORTH

CLK_TO_EXT_SOUTH

Output

This is part of the inter-byte clocking structure.

It is a copy of the data sample clock that is forwarded over dedicated routing resources to a neighboring byte BITSLICE_CONTROL or CLK_FROM_EXT clock input.

PCLK_NIBBLE_IN

NCLK_NIBBLE_IN

Input

These inputs are part of the inter-nibble clocking structure and are routed over dedicated routing resources to the N(P)CLK_NIBBLE_OUT between the upper and lower nibbles within a byte.

PCLK_NIBBLE_OUT

NCLK_NIBBLE_OUT

Output

These outputs are part of the inter-nibble clocking structure and are routed over dedicated routing resources to the N(P)CLK_NIBBLE_IN between the upper and lower nibbles within a byte.

BITSLICE_CONTROL Attributes

REFCLK_SRC

Determines what master clock input is used.

DIV_MODE

Determines the division factor of the master clock in the BITSLICE_CONTROL.

When 4 bits are used, set to DIV2.

When 8 bits are used, set to DIV4.

SELF_CALIBRATE

Determines whether or not the clock is going to be tuned to the captured data and tracked over voltage and temperature.

IDLY_VT_TRACK

ODLY_VT_TRACK

QDLY_VT_TRACK

Turn VT tracking on or off per type of delay line.

By default these attributes are turned on.

RX_CLK_PHASE_N

RX_CLK_PHASE_P

Shifts the internal capture clock by 90 degrees (or not).

When data and clock arrive phase-aligned, this attribute can be set to SHIFT_90.

When data and clock arrive 90-degrees shifted, use SHIFT_0.

EN_CLK_TO_EXT_NORTH

EN_CLK_TO_EXT_SOUTH

Enable inter-byte clocking to the north or south BITSLICE_CONTROL component.

EN_OTHER_NCLK

EN_OTHER_PCLK

Set the direction of the inter-nibble clocking. Section Clocking in Native Mode has details on how inter-nibble clocking allows clocks or strobes to be shared within a byte.

RXTX_BITSLICE Pins

FIFO_WRCLK_OUT

Output

This is a copy of the internal FIFO write clock.

The frequency of this clock is the data sample clock divided by the factor of the DIV_MODE attribute. The data sample clock can be the provided REFCLK or PLL_CLK or can be the clock or strobe provided at a BITSLICE_0.

FIFO_RD_CLK

Input

This is a clock provided by a MMCM, PLL, or other. This clock must have the same frequency as the internal bit slice FIFO write clock, but most likely it has a different phase.

RXTX_BITSLICE Attributes

OUTPUT_PHASE_90

When set to TRUE, the transmitter output is phase-shifted over 90 degrees. The phase shift can easily be observed when different transmitters are used.

This attribute is most often used to shift the generated clock 90 degrees to the generated data.

RX_DATA_WIDTH

TX_DATA_WIDTH

This attribute sets the width of the serial-to-parallel and parallel-to-serial converter. It must correspond to the DIV_MODE attribute of the BITSLICE_CONTROL.

When set to 8, DIV_MODE must be set to 4 or conversely, when DATA_WIDTH is set to 4, DIV_MODE must be set to 2.

RX_DATA_TYPE

Set to DATA when the bit slice receiver is used to capture only data. Set to DATA_AND_CLOCK (only for BITSLICE_0) when the clock can be used as a sample clock for the data (SERIAL_MODE = FALSE) and that clock is also sampled as data.

Set to SERIAL when bit slice receive data is captured by PLL_CLK.

RX_REFCLK_FREQUENCY

TX_REFCLK_FREQUENCY

This attribute must be set to the frequency applied to the BITSLICE_CONTROL master clock input (PLL_CLK or REFCLK).

There are no clocks or clock-related pins related to the bit slice transmitter. The transmitter in the RXTX_BITSLICE uses the BITSLICE_CONTROL master clock (PLL_CLK or REFCLK) to transmit data.

The transmit data rate is equal to the BITSLICE_CONTROL master clock frequency. For example, when the master clock frequency is 1000 MHz, the transmitted data rate is equal to 1 Gb/s.